This invention relates generally to radio frequency circuits and more particularly to radio frequency modulators.
As is known in the art, many electronic warfare systems and communication systems rely upon the generation of rapidly changing frequencies over a wide band of frequencies from typically under 100 MHz to tens of GHz. At the present time, the requirements for circuits to generate the rapidly changing frequencies in communication systems are concerned principally with providing sources having relatively high spectral purity for the output signal. In the electronic warfare systems, the requirements are more often driven by the ability of the source to rapidly change frequency. This characteristic of a source to rapidly change frequency is commonly referred to as "agility" or specifically "frequency agility."
Several techniques are known in the art for achieving rapidly changing frequencies over a wide band of interest. The choice of a particular technique is generally determined at least in part by the band of interest over which the system must operate and the tuning range desired to interact with the operative bandwidth. Given specific requirements for bandwidth and tuning range, each of these requirements impact system complexity by the amount of filtering needed at the output of the signal source. Further, for some broadband applications, the bandwidth is divided into a number of subbands, which have associated circuits used to generate the frequencies within the desired subband of interest. Thus, for more demanding system requirements, bandwidth and tuning range may have a significant impact on system cost and complexity.
Three techniques are presently used for providing frequency agile signals for electronic warfare and communication systems. The techniques are digital voltage controlled oscillators (DVCO), direct access synthesizers (DAS), and direct digital synthesizers (DDS).
In a digital voltage controlled oscillator (DVCO), a well characterized voltage controlled oscillator having acceptable open loop stability is controlled by a highly precise voltage source which is set to a desired voltage via a lookup table or other technique. The desired voltage is selected to have a value which is expected to produce the desired output frequency from the oscillator. Typically, the DVCO frequency is calibrated during operation or in other words "on the fly" via techniques such as beat-note counting or simple frequency counting to provide an accurate frequency representation. Recalibration at various intervals from 0.1 seconds up to 10 seconds is often used to maintain the accuracy of the calibration. While the DVCO offers high purity and relatively broadband tuning ranges, the DVCO is nevertheless large, costly, and less reliable than other approaches.
The second technique, the direct-access synthesizer includes a plurality of frequency sources which are derived from a common stable frequency reference. Each source is maintained in a circuit which feeds a switching network. The maintained frequencies are chosen so that combinations of such frequencies can be used to obtain any desired output frequency by repeatedly mixing the frequency sources and filtering the resulting frequency to provide the output frequency. That is, when a new output frequency is commanded, switches in the switch network are set to select the proper combination of maintained frequencies to feed a mixer/filter matrix of circuits and thus provide the requisite output signal frequency. The settling time of such a circuit is determined principally by the settling time of the cascade of switches, filters, and mixers. One problem with this technique is the relative complexity involved in providing the mixer/filter matrix and the difficulty required in maintaining the multitude of frequency sources.
In the third technique, the so-called direct digital synthesizer, the phase .phi.(t) of the desired output signal is calculated in real time by a circuit referred to as a phase accumulator. The phase accumulator can be thought of as a digital integrator. The phase accumulator is fed by a stable frequency clock signal having a frequency f.sub.c and a control word representing .DELTA..phi.. The value of .DELTA..phi. is chosen such that f.sub.c .DELTA..phi. is the desired output frequency. The phase accumulator includes a digital binary adder whose output is fed to a latch clocked at a frequency f.sub.c. The latch output representing .phi.(t) is fed back to the input of the adder and .DELTA..phi. is fed to the other input of the adder. The output of the phase accumulator is a binary representation of phase .phi. between 0 and 2 .pi. radians and the input of the phase accumulator is the binary representation of a phase increment .DELTA..phi. such that .phi.(t)=tf.sub.c .DELTA..phi.+(a constant). If 2.sup.N states of the binary phase accumulator corresponds exactly to 2.pi. radians of phase shift, then overflows represent errors of an integer times 2.pi. and hence do not affect the value of the output waveform since 2.pi. is the period of the waveform. The output of the phase accumulator is applied to a digital to analog converter which accepts a binary word representing .phi. and generates analog voltages proportional to sine .phi. and cosine .phi.. This type of a digital to analog converter commonly called a DASC or digital to analog sine/cosine converter has its outputs fed to a quadrature-balanced mixer, which is also fed by a local oscillator (LO) to produce a modulated local oscillator frequency to provide the desired RF output frequency.
There are several implementations of the digital/analog sine converter. For example, one implementation simply may employ a read only memory (ROM) with each binary word of phase corresponding to an address in the ROM and each word of the ROM corresponding to the binary representation of the sine or cosine function of the address of that word. The output of the ROM, accordingly, is the digital representation of sine .phi. or cosine .phi. and when applied to a linear digital-to-analog converter results in an analog waveform. A ROM-DAC-based system would require the use of large ROMs to provide acceptable waveform accuracy and spectral purity. Moreover, throughput (i.e. tuning range) is more limited than with other approaches. Further, since a ROM is a large, complex digital part it would not be a good candidate for integration with microwave analog circuits on a common integrated semiconductor chip, particularly GaAs.
A second implementation of the sine converter, which is faster but less accurate than the ROM-DAC system described above is to use specially designed non-linear DACs which implement the digital to analog sine functions directly. The problem with this system is that a DASC of more than 7 or 8 bits of phase resolution is extremely large and thus a DASC is not preferred where high accuracy is required. Furthermore, even an 8-bit DASC is a circuit of VLSI complexity and is difficult to integrate with microwave circuitry on one chip.
Both of the above approaches (ROM-DAC and DASC) are only applicable to baseband frequencies less than f.sub.c. The upconversion (mixing) needed to generate RF generates spurious frequencies which must be filtered out thus limiting the bandwidth and greatly increasing system complexity.